Rachman, Syaiful (2013) Desain dan Analisis Integrated Circuit Transistor Transistor Logic and Or Inverter Dual 2-Wide 2-Input Kecepatan Tinggi. Magister thesis, Universitas Brawijaya.
Abstract
Rangkaian terpadu ( Integrated Circuit ) gerbang logika standard TTL AOI ( And Or Inverter ) Dual 2-Wide 2-Input berdasarkan kecepatan operasi gerbang digital meliputi parameter waktu t PLH ( transisi low to high ), t PHL ( transisi high to low ) dan time propagation delay average (tPD) dapat ditingkatkan kecepatannya dengan rangkaian aktif base recovery pull-down dan aktif pull-up pseudo Darlington sebagai rangkaian high speed TTL. Tujuan penelitian yaitu mendesain dan menganalisis kinerja rangkaian terpadu (integrated circuit) TTL AOI Dual 2-Wide 2-Input menggunakan rangkaian aktif base recovery ( pull-down ) dan pseudo Darlington ( pull-up ), yang dikategorikan sebagai rangkaian high speed TTL dengan perbandingan rangkaian standard , sehingga dapat memperkecil time propagation delay (tPD) dan diperoleh karakteristik transfer alih tegangan (VTC) lebih ideal. Spesifikasi hasil simulasi menggunakan Program PSPICE dengan kapasitor beban, C L = 15 pf dan menghasilkan transisi low to high sebesar 0,94 ns, transisi high to low adalah 0,49 ns sehingga waktu rerata propagasi yang dihasilkan sebesar 0,72 ns dan transfer karakteristik alih tegangan (VTC) yaitu V IL = 1,3V; V IH = 1,53V ; V OL = 0,062V; V OH = 3,42V dengan Noise Margin N MH = 1,89V dan N ML = 1,24 V, sedangkan disipasi daya yang diperoleh 31,45 mW. Hasil perhitungan dan simulasi menunjukkan peningkatan kecepatan yang dihasilkan dibandingkan rangkaian standard TTL AOI dan datasheet SN54S51. Sedangkan penggambaran layout dengan I/O pad menggunakan program Microsoft Visio 2007 dengan memiliki luasan 19,50 mm x 9,36 mm.
English Abstract
operating speed of IC TTL AOI Dual 2-Wide 2-Input can be increased using a series of active base recovery pull-down and active pull-up pseudo Darlington. objective was to design and analyze performance of IC TTL AOI Dual 2-Wide 2-Input using active base recovery and pseudo Darlington, which was classified as highspeed TTLS. voltage transfer characteristics (VTC) was expected to be more ideal, and less propagation delay time (t PD ) could be obtained. Simulation results using PSPICE and load capacitor, CL = 15 pf, produced low to high transition time of 0.94 ns and high to low transition time of 0.49 ns. average propagation time was 0.72 ns, with Noise Margin N MH = 1.89 V and N ML = 1.24 V. Power dissipation was 31.45 mW. simulation showed increase in operating speed compared to standard TTL series datasheet AOI and SN54S51.
| Item Type: | Thesis (Magister) |
|---|---|
| Identification Number: | TES/621.381 5/RAC/d/041302609 |
| Subjects: | 600 Technology (Applied sciences) > 621 Applied physics > 621.3 Electrical, magnetic, optical, communications, computer engineering; electronics, lighting |
| Divisions: | S2/S3 > Magister Teknik Elektro, Fakultas Teknik |
| Depositing User: | Endro Setyobudi |
| Date Deposited: | 27 Jun 2013 14:36 |
| Last Modified: | 27 Jun 2013 14:36 |
| URI: | http://repository.ub.ac.id/id/eprint/158670 |
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