Mannan, ArifAbdul (2013) Design And Analysis Of Asynchronous Delta-Sigma Modulators Using Multiple-Valued Logic. Magister thesis, Universitas Brawijaya.
Abstract
Dalam master ini SIS, modulator delta-sigma asinkron dengan output multi-nilai disajikan. Untuk mengimplementasikan modulator Δς asinkron dengan logika multi-nilai, pembanding histeresis multi-nilai diperlukan. Inverter multi-nilai Fur R Lmore diperlukan untuk mengimplementasikan pembanding histeresis multi-nilai. Tiga inverter multi-nilai dan empat pembanding histeresis multi-nilai disajikan. Selanjutnya, menggunakan sirkuit SE, modulator delta-sigma asinkron dengan output multi-nilai (MADSM) dirancang. MADSM beroperasi sebagai N-1 Jumlah Sirkuit Modulator Binary Asynchronous Delta-Sigma (BADSM) bertumpuk. Kesalahan oretik untuk Sirkuit Modulator Delta-Sigma Asinkron (ADSM) dihitung dan dibahas. Perhitungan kesalahan oretik terdiri dari lima aspek komponen non idealitas seperti penundaan propagasi komparator, naik dan penundaan OTA, dll. Terakhir analog-to-digital (ADC) dirancang sebagai aplikasi MADSM yang diusulkan. Sirkuit Madsm dikombinasikan dengan sirkuit MDDC (MVL Decoder dan Digital Counter) untuk mewujudkan ADC. Sirkuit ADC digunakan untuk mengevaluasi hasil perhitungan kesalahan oretik. Dari aplikasi Madsm pada sirkuit ADC, kinerja sirkuit yang diusulkan adalah output digital 10-bit dengan frekuensi pengambilan sampel 50 KHZ dan - 60.8DBV lantai kebisingan untuk ADC dan -70.4dbv untuk MADSM ketika sirkuit dirancang dengan menggunakan proses CMOS standar .,0μm.
English Abstract
In this master sis, asynchronous delta-sigma modulator with multi-valued output is presented. In order to implement asynchronous ΔΣ modulator with multi-valued logic, multi-valued hysteresis comparator is required. Fur rmore multi-valued inverter is necessary to implement multi-valued hysteresis comparator. Three multi-valued inverters and four multi-valued hysteresis comparators are presented. Next, using se circuits, asynchronous delta-sigma modulator with multi-valued output (MADSM) is designed. MADSM operates as n-1 number of stacked binary asynchronous delta-sigma modulator ( BADSM) circuit. oretical error for asynchronous delta-sigma modulator (ADSM) circuit is calculated and discussed. oretical error calculation consists of five aspects of component non ideality such as propagation delay of comparator, rise and fall delays of OTA, etc. Lastly analog-to-digital converter (ADC) is designed as an application of proposed MADSM. MADSM circuit is combined with MDDC (MVL Decoder and Digital Counter) circuit to realize ADC. ADC circuit is utilized to evaluate oretical error calculation result. From MADSM application on ADC circuits, proposed circuit performance is 10-bit digital output with 50 kHz sampling frequency and - 60.8dBV noise floor for ADC and -70.4dBV for MADSM when circuits are designed by using 2.0μm standard CMOS process.
| Item Type: | Thesis (Magister) |
|---|---|
| Identification Number: | TES/621.382 16/MAN/d/041310661 |
| Subjects: | 600 Technology (Applied sciences) > 621 Applied physics > 621.3 Electrical, magnetic, optical, communications, computer engineering; electronics, lighting |
| Divisions: | S2/S3 > Magister Teknik Elektro, Fakultas Teknik |
| Depositing User: | Budi Wahyono Wahyono |
| Date Deposited: | 12 May 2014 14:41 |
| Last Modified: | 12 May 2014 14:41 |
| URI: | http://repository.ub.ac.id/id/eprint/158680 |
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